1. Field of the Invention
The invention generally relates to integrated circuit (IC) fabrication, and more particularly relates to a method for fabricating a dynamic random access memory (DRAM) cell capacitor, whose bottom electrode plate is provided with a plurality of islands in its surface for increasing its capacitance.
2. Description of the Related Art
Dynamic random access memory (DRAM) composed of a number of memory cells arranged in array is widely utilized in digital electronic equipment. A conventional memory cell located within the DRAM, as shown in FIG. 1A, comprises metal-oxide semiconductor field-effect transistor (MOSFET) 6 and capacitor 8. The gate region of MOSFET 6 is connected to a word line designated as WL. A pair of source/drain regions are connected to the ground node through capacitor 8 and a bit line designated as BL, respectively. Capacitor 8 is used to store the data and should be provided with enough capacitance to prevent data loss.
A stacked capacitor is a commonly used structure in DRAM cells. Referring to FIG. 1B, field oxide 11, gate electrode 12, and source/drain regions 18 are formed on silicon substrate 10. Silicon dioxide layer 13 is deposited over gate electrode 12 and source/drain regions 18, wherein a contact opening is formed to expose the desired portion of source/drain regions 18. First polysilicon layer 14 (bottom electrode plate of the stacked capacitor), dielectric layer 15, such as nitride/oxide (NO) or oxide/nitride/oxide (ONO) layers, and second polysilicon layer 16 (top electrode plate of the stacked capacitor) are next formed on silicon dioxide layer 13, respectively, so as to construct a cell capacitor. First polysilicon layer 14 is connected with desired source/drain regions 18 through contact opening 130 within silicon dioxide layer 13. Finally, a borophosphosilicate glass (BPSG) 17 is deposited over the cell capacitor serving as a passivation layer. Then, a metal layer 19 is sequentially deposited to contact with one of the source/drain regions 18 via a contact opening thereof.
Since the device density on integrated circuits is now approaching that of VLSI, or even ULSI, the feature size of the DRAM cell is getting smaller, resulting in a smaller capacitor and hence less capacitance. Hence, there are two methods to increase the capacitance: (I) decrease the effective dielectric thickness and (II) increase surface area of the electrode plate of the capacitor. When the effective dielectric thickness is decreased, however, greater capacitance can be obtained but seriously degrading the device retention time because dielectric films thinner than 50 .ANG. presently have excessive leakage currents attributed to direct carrier tunneling. For a given capacitor dielectric film, the larger the surface area of the storage electrodes, the higher the capacitance. Using trenched capacitors for DRAM cells is another scheme for increasing capacitance. The trenched capacitor is formed within a trench nearby a transistor device. However, this kind of capacitor suffers from a reduced etch rate for high-aspect-ratio trenches, and thus the processing requires massive amounts of time and hence is expensive. Also, inevitable crystalline defects occur by means of this process.